Semiconductor die density has continuously increased, and continues to increase. Further miniaturization and increased density in semiconductor dies require an increasing number of signal, ground and power electrical interconnects and connections. To make efficient use of limited surface area on semiconductor dies, conventional methods have included forming interconnects within the semiconductor dies using through wafer vias (TWVs). Conventional TWVs may, for example, connect a ground plane on a bottom surface of a semiconductor die with circuitry on a top surface of a semiconductor die. However, such conventional TWVs are typically very wide, for example, 50 μm (micrometers) in diameter. Such large widths result in undesirable characteristics in semiconductor dies and their semiconductor substrates. For example, placement of numerous conventional TWVs within a semiconductor substrate can result in a significant reduction in mechanical stability of the semiconductor substrate. Thus, the number and density of such conventional TWVs placed within a semiconductor substrate must be limited. Such limitations result in large minimum distances between TWVs and semiconductor devices, such as transistors, situated in a semiconductor die.
Moreover, utilizing a small number of conventional TWVs results in an uneven thermal dissipation within the semiconductor substrate, especially during high power operation. The uneven thermal dissipation can result in increased thermal stress in the semiconductor substrate, thus reducing mechanical stability and reliability of the semiconductor die.
Further, although it is desirable to completely fill TWVs with conductive material, conventional fabrication methods result in incomplete filling of the TWVs, especially at their top and bottom portions. The incomplete filling can result in unwanted gaps in the top and bottom portions of the TWVs which can, for example, lead to contamination of the TWVs during subsequent processes.